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Языки описания аппаратуры, FPGA и CPLD

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MIL-1553b [May. 10th, 2007|11:30 pm]
Языки описания аппаратуры, FPGA и CPLD

ru_hdl_fpga

[slonok]
Кто нибудь занимался вопросами декодирования/кодирование этого интерефейса (Манчестер-2)?
Интерисует логическая схема или алгоритм.
linkReply

Comments:
[User Picture]From: holy_glory
2007-05-11 08:40 am (UTC)
Manchester II, декодер (за частоту захватывается сам, рабочая частота должна быть раз в 6-8 выше частоты передачи).

//Вспомогательный модулек
// Module HolyGlory.manch_corr.struct
//
// Created:
// by - Lisin.UNKNOWN (ASYSD)
// at - 19:59:48 28.07.2005
//
// Generated by Mentor Graphics' HDL Designer(TM) 2004.1b (Build 12)
//

`resetall
`timescale 1ns/10ps
module manch_corr(
i_clk,
i_cor_done,
i_rst,
i_rx,
o_bit_fix,
o_last_bit,
o_progress
);


// synopsys template
parameter T = 1,
CNTWS = 4;

// Internal Declarations

input i_clk;
input i_cor_done;
input i_rst;
input i_rx;
output o_bit_fix;
output o_last_bit;
output o_progress;


wire i_clk;
wire #T i_cor_done;
wire #T i_rst;
wire i_rx;
wire o_bit_fix;
wire o_last_bit;
reg o_progress;

// Local declarations
// Non hierarchical state machine declarations
// Module Declarations
// State encoding
parameter [2:0] // pragma enum CRM_CS_code
CRM_IDLE = 3'd0 ,
CRM_MES = 3'd1 ,
CRM_FMES = 3'd2 ,
CRM_WCNT = 3'd3 ,
CRM_WE = 3'd4 ,
CRM_FINISH = 3'd5 ;

reg [2:0] /* pragma enum CRM_CS_code */ CRM_CS, CRM_NS ;
// pragma state_vector CRM_CS


// Internal signal declarations
reg [CNTWS:0] LCNT;
reg [CNTWS-1:0] WCNT;
reg acce;
reg cnt_ovf;
reg cnt_wr;
reg [CNTWS:0] crcnt;
reg cur_bit;
reg dedge;
reg rx_cld;


// Instances
// HDL Embedded Text Block 1 FF
// FF 1
always @(posedge i_clk)
rx_cld <= #T i_rx;

always @(posedge i_clk)
dedge <= #T i_rx^rx_cld;

always @(posedge i_clk)
cur_bit <= #T rx_cld&~i_rx;
// HDL Embedded Text Block 2 crr
// crr 2
always @(posedge i_rst or posedge i_clk)
if (i_rst)
WCNT[CNTWS-1:0] <= #T 0;
else
if (rx_cld)
WCNT[CNTWS-1:0] <= #T WCNT[CNTWS-1:0] + 1;
else
WCNT[CNTWS-1:0] <= #T 0;
// HDL Embedded Text Block 3 CNT_L
// CNT_L 3
reg [CNTWS:0] WCNTP;

always @(posedge i_clk)
WCNTP[CNTWS:0] <= #T WCNT[CNTWS-1:0]+WCNT[CNTWS-1:1];


always @(posedge i_clk or posedge i_rst)
if (i_rst)
LCNT[CNTWS:0] <= #T 0;
else
if (cnt_wr)
LCNT[CNTWS:0] <= #T WCNTP[CNTWS:0];

(Reply) (Thread)
[User Picture]From: holy_glory
2007-05-11 08:41 am (UTC)
// HDL Embedded Block 4 CRM
// Non hierarchical state machine
//-----------------------------------------------------------------
// Next State Block for machine machine1
//-----------------------------------------------------------------
always @(
CRM_CS or
cnt_ovf or
dedge or
i_cor_done or
rx_cld)
begin
case (CRM_CS)
CRM_IDLE:
if (rx_cld)
CRM_NS = CRM_MES;
else
CRM_NS = CRM_IDLE;
CRM_MES:
if (~rx_cld)
CRM_NS = CRM_FMES;
else
CRM_NS = CRM_MES;
CRM_FMES:

CRM_NS = CRM_WCNT;

CRM_WCNT:
if (cnt_ovf| dedge)
CRM_NS = CRM_WE;
else
CRM_NS = CRM_WCNT;
CRM_WE:
if (dedge)
CRM_NS = CRM_WCNT;
else
CRM_NS = CRM_WE;
CRM_FINISH:
if (~rx_cld)
CRM_NS = CRM_IDLE;
else
CRM_NS = CRM_FINISH;
default: begin
CRM_NS = CRM_IDLE;
end
endcase

// Interrupts
if (i_cor_done) CRM_NS = CRM_FINISH;
end // Next State Block

//-----------------------------------------------------------------
// Output Block for machine machine1
//-----------------------------------------------------------------
always @(
CRM_CS)
begin
// Default Assignment
acce = 0;
cnt_wr = 0;
o_progress = 1;
// Default Assignment To Internals

// Combined Actions
case (CRM_CS)
CRM_IDLE: begin
o_progress = 1'b0;
end
CRM_MES: begin
acce = 1'b1;
end
CRM_FMES: begin
cnt_wr = 1'b1;
end
CRM_WE: begin
acce = 1'b1;
end
CRM_FINISH: begin
o_progress = 1'b0;
end
endcase


end // Output Block

//-----------------------------------------------------------------
// Clocked Block for machine machine1
//-----------------------------------------------------------------
always @(
posedge i_clk or posedge i_rst
) begin
if (i_rst) begin
CRM_CS <= CRM_IDLE;
// Reset Values
end
else
begin
CRM_CS <= CRM_NS;
// Default Assignment To Internals
end
end // Clocked Block

// Concurrent Statements


// HDL Embedded Text Block 5 rcor
// rcor 5


reg r_cr;
always @(posedge i_clk)
r_cr <= #T acce&dedge;


always @(posedge i_clk or posedge i_rst)
if (i_rst)
crcnt[CNTWS:0] <= #T 3;
else
if (r_cr)
crcnt[CNTWS:0] <= #T 3;
else
crcnt[CNTWS:0] <= #T crcnt[CNTWS:0] + 1;

always @(posedge i_clk)
cnt_ovf <= #T (crcnt[CNTWS:0]==LCNT[CNTWS:0]) ? ~cnt_wr : 0;


reg r_cur_bit;


always @(posedge i_clk) r_cur_bit <= #T cur_bit;

reg r_bit_fix;

always @(posedge i_clk)
r_bit_fix <= #T r_cr;

assign o_bit_fix = r_bit_fix;

assign o_last_bit = r_cur_bit;

endmodule // manch_corr



(Reply) (Parent) (Thread)
[User Picture]From: holy_glory
2007-05-11 08:42 am (UTC)

// Сам десериалайзер
// Module HolyGlory.Manchester_deser.struct_v2
//
// Created:
// by - user_08.UNKNOWN (LISIN)
// at - 15:42:51 04.10.2006
//
// Generated by Mentor Graphics' HDL Designer(TM) 2004.1b (Build 12)
//

`resetall
`timescale 1ns/10ps
module Manchester_deser(
i_clk,
i_frx,
i_rst,
o_data,
o_data_rdy,
o_line_interrupted,
o_parity,
o_rc_process
);


// synopsys template
parameter T = 1,
CNTWS = 3, //Размер счетчика, захватывающего приемный сигнал
DATA_WIDTH = 16, //Ширина принимаемого слова, включая бит четности
WD_WIDTH = 4, //Ширина счетчика вотч-дога, регистрирующего обрыв линии/потерю связи
WD_VAL = 0; //Значение, при котором вотчдог срабатывает

// Internal Declarations

input i_clk;
input i_frx;
input i_rst;
output [DATA_WIDTH-1:0] o_data;
output o_data_rdy;
output o_line_interrupted;
output o_parity;
output o_rc_process;


wire i_clk;
wire #T i_frx;
wire #T i_rst;
wire [DATA_WIDTH-1:0] #T o_data;
wire #T o_data_rdy;
wire #T o_line_interrupted;
wire #T o_parity;
wire #T o_rc_process;

// Local declarations

// Internal signal declarations
wire ISprocess;
wire #T WD_EXIT;
wire #T cor_done;
wire ints_bit_fix;
wire ints_last_bit;
reg [DATA_WIDTH:0] sh_data_reg;


// Instances
manch_corr #(T,CNTWS) corr(
.i_clk (i_clk),
.i_cor_done (cor_done),
.i_rst (i_rst),
.i_rx (i_frx),
.o_bit_fix (ints_bit_fix),
.o_last_bit (ints_last_bit),
.o_progress (ISprocess)
);

// HDL Embedded Text Block 4 Act
// Act 4
reg ISprocess_cld;

assign o_rc_process = ISprocess_cld;

always @(posedge i_clk or posedge i_rst)
if (i_rst)
ISprocess_cld <= #T 1'b0;
else
ISprocess_cld <= #T ISprocess;
// HDL Embedded Text Block 5 Line_dead
// Line_dead 5

reg [WD_WIDTH : 0] WD_CNT;

reg wd_res;
always @(posedge i_clk)
wd_res <= #T (ints_bit_fix|~ISprocess);

always @(posedge i_clk or posedge i_rst)
if (i_rst)
WD_CNT[WD_WIDTH : 0] <= #T 0;
else
WD_CNT[WD_WIDTH : 0] <= #T (wd_res)? 0 : //Reset watch-dog, if event occured
WD_CNT[WD_WIDTH-1 : 0] + 1; //Increment it until event

wire #T ints_wd_ovf;
assign ints_wd_ovf = (WD_VAL==0) ? WD_CNT[WD_WIDTH] : ((WD_CNT[WD_WIDTH-1:0]==WD_VAL) ? 1'b1 : 1'b0);

assign o_line_interrupted = ints_wd_ovf;
assign WD_EXIT = ints_wd_ovf;
// HDL Embedded Text Block 7 Deser
// Deser 7

reg par_reg;


reg [DATA_WIDTH:0] sh_nxt;

always @(posedge i_clk)
sh_nxt[DATA_WIDTH:0] <= #T {sh_data_reg[DATA_WIDTH-1:0], ints_last_bit};

reg sh_clr;

always @(posedge i_clk)
sh_clr <= #T ((sh_data_reg[DATA_WIDTH-1]&ints_bit_fix)|~ISprocess);

always @(posedge i_clk or posedge i_rst)
if (i_rst)
sh_data_reg[DATA_WIDTH:0] <= #T 0;
else
if (ints_bit_fix)
sh_data_reg[DATA_WIDTH:0] <= #T sh_nxt[DATA_WIDTH:0];
else
if (sh_clr)
sh_data_reg[DATA_WIDTH:0] <= #T 0;



always @(posedge i_clk or posedge i_rst)
if (i_rst)
par_reg <= #T 1'b0;
else
if (~ISprocess)
par_reg <= #T 1'b0;
else
if (ints_bit_fix)
par_reg <= #T par_reg ^ sh_nxt[0];



assign cor_done = sh_data_reg[DATA_WIDTH]|WD_EXIT;
assign o_data_rdy = sh_data_reg[DATA_WIDTH];
assign o_data[DATA_WIDTH-1:0] = sh_data_reg[DATA_WIDTH-1:0];
assign o_parity = par_reg;

endmodule // Manchester_deser


(Reply) (Parent) (Thread)
[User Picture]From: holy_glory
2007-05-11 08:44 am (UTC)


А это собсна сам кодер:

//
// Module HolyGlory.Manchester_ser.strr2
//
// Created:
// by - Lisin.UNKNOWN (ASYSD)
// at - 15:41:33 05.05.2006
//
// Generated by Mentor Graphics' HDL Designer(TM) 2004.1b (Build 12)
//

`resetall
`timescale 1ns/10ps
module Manchester_ser(
i_clk,
i_data, //Собсна че передаем
i_data_wr, //строб передаче того, что на входе i_data
i_parity_en, //Передавать ли четность
i_rst,
o_TX,
o_TX_en
);


// synopsys template
parameter T = 1,
DATA_WIDTH_CNT_WIDTH = 4, //Размер счетчика нмера передаваемого бита
DATA_WIDTH = 16, //Размер передаваемого слова, не считая бита четности
CLK_DIV_VALUE = 4'hA, //То, на сколько делим входной клок при передачи. Boudrate = I_clk_freq/(CLK_DIV_VALUE+1)/2
CLK_DIV_WIDTH = 4;

// Internal Declarations

input i_clk;
input [DATA_WIDTH-1:0] i_data;
input i_data_wr;
input i_parity_en;
input i_rst;
output o_TX;
output o_TX_en;


wire i_clk;
wire [DATA_WIDTH-1:0] #T i_data;
wire #T i_data_wr;
wire i_parity_en;
wire #T i_rst;
wire o_TX;
wire o_TX_en;

// Local declarations
// Non hierarchical state machine declarations
// Module Declarations
// State encoding
parameter [2:0] // pragma enum machine1_current_state_code
TX_IDLE = 3'd0 ,
TX_TR = 3'd1 ,
TX_TR_LAST = 3'd2 ,
TX_TR_PARITY = 3'd3 ,
TX_TR_Blank = 3'd4 ,
TX_START = 3'd5 ;

reg [2:0] /* pragma enum machine1_current_state_code */ machine1_current_state, machine1_next_state ;
// pragma state_vector machine1_current_state


// Internal signal declarations
reg [CLK_DIV_WIDTH-1:0] clkd_cnt;
wire cur_bit;
reg d_bnxt;
reg [DATA_WIDTH_CNT_WIDTH-1:0] dcnt;
reg ints_clk;
reg ints_clk_d1;
wire #T ints_last_bit;
reg r_parity;
wire #T sh_data;
reg [DATA_WIDTH:0] sh_reg;
reg tx_active;
reg tx_enable;
reg tx_par_sel;


// Instances
// HDL Embedded Text Block 1 sh_reg_eb
// sh_reg_eb 1

always @(posedge i_clk or posedge i_rst)
if (i_rst)
sh_reg[DATA_WIDTH:0] <= #T 0;
else
if (i_data_wr)
sh_reg[DATA_WIDTH:0] <= #T {1'b1, i_data[DATA_WIDTH-1:0]};
else
if (d_bnxt)
sh_reg[DATA_WIDTH:0] <= #T {sh_reg[DATA_WIDTH-1:0], 1'b0};
else
sh_reg[DATA_WIDTH:0] <= #T sh_reg[DATA_WIDTH:0];


assign sh_data = sh_reg[DATA_WIDTH];


always @(posedge i_clk or posedge i_rst)
if (i_rst)
dcnt[DATA_WIDTH_CNT_WIDTH-1:0] <= #T 0;
else
if (i_data_wr)
dcnt[DATA_WIDTH_CNT_WIDTH-1:0] <= #T DATA_WIDTH;
else
if (d_bnxt)
dcnt[DATA_WIDTH_CNT_WIDTH-1:0] <= #T dcnt[DATA_WIDTH_CNT_WIDTH-1:0] - 1;

assign ints_last_bit = (dcnt[DATA_WIDTH_CNT_WIDTH-1:0]==0) ? 1 : 0;
(Reply) (Parent) (Thread)
[User Picture]From: holy_glory
2007-05-11 08:46 am (UTC)
// HDL Embedded Text Block 2 tx_blk
// tx_blk 2

wire #T clk_inv;

assign clk_inv = (clkd_cnt[CLK_DIV_WIDTH-1:0]==CLK_DIV_VALUE) ? 1 : 0;

always @(posedge i_clk or posedge i_rst)
if (i_rst)
clkd_cnt[CLK_DIV_WIDTH-1:0] <= #T 0;
else
if (tx_active)
begin
if (clk_inv)
clkd_cnt[CLK_DIV_WIDTH-1:0] <= #T 0;
else
clkd_cnt[CLK_DIV_WIDTH-1:0] <= #T clkd_cnt[CLK_DIV_WIDTH-1:0] + 1;
end
else
clkd_cnt[CLK_DIV_WIDTH-1:0] <= #T 0;


always @(posedge i_clk or posedge i_rst)
if (i_rst)
ints_clk <= #T 1'b0;
else
if (tx_active)
begin
if (clk_inv) ints_clk <= #T ~ints_clk;
end
else
ints_clk <= #T 1'b0;

always @(posedge i_clk)
ints_clk_d1 <= #T ints_clk;


always @(posedge i_clk or posedge i_rst)
if (i_rst)
r_parity <= #T 1'b0;
else
if (tx_active)
begin
if (clk_inv&ints_clk)
r_parity <= #T r_parity^sh_data;
end
else
r_parity <= #T 1'b0;

always @(posedge i_clk)
d_bnxt <= #T clk_inv&ints_clk;

reg r_tx;

always @(posedge i_clk)
if (tx_enable)
r_tx <= #T cur_bit^ints_clk_d1;
else
r_tx <= #T 1'b0;

assign o_TX = r_tx;

//reg r_tx_en;
//
//always @(posedge i_clk)
// r_tx_en <= tx_active;

assign o_TX_en = tx_active;
// HDL Embedded Text Block 3 eb1
// eb1 3
assign cur_bit = (tx_par_sel) ? r_parity : sh_data;
// HDL Embedded Block 4 TXSM
// Non hierarchical state machine
//-----------------------------------------------------------------
// Next State Block for machine machine1
//-----------------------------------------------------------------
always @(
d_bnxt or
i_data_wr or
i_parity_en or
ints_last_bit or
machine1_current_state)
begin
case (machine1_current_state)
TX_IDLE:
if (i_data_wr)
machine1_next_state = TX_START;
else
machine1_next_state = TX_IDLE;
TX_TR:
if (ints_last_bit)
machine1_next_state = TX_TR_LAST;
else
machine1_next_state = TX_TR;
TX_TR_LAST:
if (d_bnxt& i_parity_en)
machine1_next_state = TX_TR_PARITY;
else if (d_bnxt)
machine1_next_state = TX_TR_Blank;
else
machine1_next_state = TX_TR_LAST;
TX_TR_PARITY:
if (d_bnxt)
machine1_next_state = TX_TR_Blank;
else
machine1_next_state = TX_TR_PARITY;
TX_TR_Blank:
if (d_bnxt)
machine1_next_state = TX_IDLE;
else
machine1_next_state = TX_TR_Blank;
TX_START:

machine1_next_state = TX_TR;

default: begin
machine1_next_state = TX_IDLE;
end
endcase

end // Next State Block

(Reply) (Parent) (Thread)
[User Picture]From: holy_glory
2007-05-11 08:46 am (UTC)
//-----------------------------------------------------------------
// Output Block for machine machine1
//-----------------------------------------------------------------
always @(
machine1_current_state)
begin
// Default Assignment
tx_active = 0;
tx_enable = 0;
tx_par_sel = 0;
// Default Assignment To Internals

// Combined Actions
case (machine1_current_state)
TX_TR: begin
tx_enable = 1'b1;
tx_active = 1'b1;
end
TX_TR_LAST: begin
tx_enable = 1'b1;
tx_active = 1'b1;
end
TX_TR_PARITY: begin
tx_active = 1'b1;
tx_enable = 1'b1;
tx_par_sel = 1'b1;
end
TX_TR_Blank: begin
tx_active = 1'b1;
end
TX_START: begin
tx_active = 1'b1;
end
endcase


end // Output Block

//-----------------------------------------------------------------
// Clocked Block for machine machine1
//-----------------------------------------------------------------
always @(
posedge i_clk or posedge i_rst
) begin
if (i_rst) begin
machine1_current_state <= TX_IDLE;
// Reset Values
end
else
begin
machine1_current_state <= machine1_next_state;
// Default Assignment To Internals
end
end // Clocked Block

// Concurrent Statements


endmodule // Manchester_ser
(Reply) (Parent) (Thread)
[User Picture]From: holy_glory
2007-05-11 08:48 am (UTC)
Ссори што без коментов

в качестве тест-бенча залупни выходкодера на декодер, и поиграй с клоками.
Декодер, еще раз, не знает о том, на какой скорости ему будут передаваться данные. Он просто захватываетс я за длину стартового бита, умножает ее на 1.5 и с таким дискретом ищет фронтики.
(Reply) (Parent) (Thread)
[User Picture]From: slonok
2007-05-11 02:53 pm (UTC)
спасибо за варианты....вопрос есть...
во сколько примерно макроячеек на Altere может декодер влесть?
у меня в схемной реализации получалось примерно 64...

это так мне для сравнения...=))
(Reply) (Parent) (Thread)
[User Picture]From: holy_glory
2007-05-11 03:00 pm (UTC)
Я не работал с альтерой. И целью оптимизация не ставилась, + вы не указали какими словами передаются данные (размер), на какой частоте, какова рабочая частота приемной части, и знает ли приемник о скорости передатчика.
Могу в качестве сравнения выкинуть высокочастотный декодер манчестера, который принимает данные с баудрейтом clk/4(5). Там он жрет меньше 30 ячеек актeл-проасика.
(Reply) (Parent) (Thread)
[User Picture]From: holy_glory
2007-05-11 03:01 pm (UTC)
Пардон.
Этот приеник оптимизирован по частоте работы а не по дайсайзу
(Reply) (Parent) (Thread)
[User Picture]From: holy_glory
2007-05-11 03:03 pm (UTC)
Вообщем вот он. Принимает битовый поток на баудрейте clk/4. В проасике работает на частоте 150мгц (практически технологический предел).

//
// Module HolyGlory.HFd5SDSER.struct6s
//
// Created:
// by - Lisin.UNKNOWN (ASYSD)
// at - 11:37:41 17.05.2006
//
// Generated by Mentor Graphics' HDL Designer(TM) 2004.1b (Build 12)
//

`resetall
`timescale 1ns/10ps
module HFd5SDSER(
i_clk,
i_rst,
i_rx,
o_bit,
o_rdy,
o_sync
);


// synopsys template
parameter T = 1;

// Internal Declarations

input i_clk;
input i_rst;
input i_rx;
output o_bit;
output o_rdy;
output o_sync;


wire i_clk;
wire #T i_rst;
wire #T i_rx;
wire #T o_bit;
wire #T o_rdy;
wire #T o_sync;

// Local declarations

// Internal signal declarations


// Instances
// HDL Embedded Text Block 1 hf_aligner
// hf_aligner 1

`define HF_A___SYNC


reg r_rx_d0;

always @(posedge i_clk)
r_rx_d0 <= #T i_rx;

reg r_rx;

always @(posedge i_clk)
r_rx <= #T r_rx_d0;

reg r_rx_edge;

always @(posedge i_clk)
r_rx_edge <= #T r_rx_d0^r_rx;

reg r_sync;
always @(posedge i_clk)
r_sync <= #T r_rx_edge;

assign o_sync = r_sync;

reg [5:0] r_rx_dsh;

`ifdef HF_ASYNC
always @(posedge i_clk or posedge r_rx_edge) // to do - i_rst
if (r_rx_edge)
r_rx_dsh[5:0] <= #T 6'h1;
else
r_rx_dsh[5:0] <= #T {r_rx_dsh[4:0], r_rx_dsh[5]};
//{1'b0, r_rx_dsh[2:0], r_rx_dsh[3]};

`else

always @(posedge i_clk or posedge i_rst)
// r_rx_dsh[4:0] <= #T (r_rx_edge) ? 5'h1 : {r_rx_dsh[3:0], r_rx_dsh[4]}; /* synthesis syn_preserve = 1 */
if (i_rst)
r_rx_dsh[5:0] <= 6'h1;
else
r_rx_dsh[5:0] <= #T (r_rx_edge) ? 6'h1 : {r_rx_dsh[4:0], r_rx_dsh[5]}; /* synthesis syn_preserve = 1 */
//r_rx_dsh[4:0] <= #T (r_rx_edge) ? 5'h1 : {1'b0, r_rx_dsh[2:0], r_rx_dsh[3]}; /* synthesis syn_preserve = 1 */

`endif

reg r_fix;
always @(posedge i_clk)
r_fix <= #T r_rx_dsh[2]&~r_rx_edge;

reg r_dtam2;

always @(posedge i_clk)
r_dtam2 <= #T r_rx;


reg r_dtam1;

always @(posedge i_clk)
r_dtam1 <= #T r_dtam2;

reg r_dta;

always @(posedge i_clk)
r_dta <= #T r_dtam1;




reg r_rdy;

always @(posedge i_clk)
r_rdy <= #T r_fix;

assign o_bit = r_dta;
assign o_rdy = r_rdy;










endmodule // HFd5SDSER

(Reply) (Parent) (Thread)
[User Picture]From: slonok
2007-05-27 02:23 pm (UTC)
спасибо большое....тока мне hdl учить ещё и учить...я так реализовал-просто, в схемотехническом варианте..
(Reply) (Thread)
[User Picture]From: kincajou
2007-05-27 02:39 pm (UTC)
дык схему перевести в HDL проще простого. Ну, относительно.
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